1. Field of the Invention
This invention relates generally to integrated circuits and more particularly to boundary scan cells used for boundary scan testing.
2. Description of the Related Art
Electronic systems typically have one or more printed circuit boards (PCBs) and one or more integrated circuit chips (“chips”). Chips typically include input/output (I/O) pins that are commonly coupled to interconnects of a PCB. Testing the performance of electronic systems, which include PCBs and chips typically require testing at chip level, at board level, and at system level. Testing at board level includes testing interconnects of the PCB. Testing at system level includes analysis of interconnections between chips, PCBs, and other devices.
In order to enhance the testability at board level and system level, a common design practice at chip level now includes incorporating IEEE Standard 1149.1 logic, or Joint Test Action Group (JTAG) logic. In order to incorporate JTAG logic, boundary scan (BS) cells are inserted for all I/O signals and control (i.e., enable) signals for tri-state outputs in the chip design. FIG. 1 is an illustration showing a partial circuit design 100A including a core 101 that communicates with I/O logic to establish a path to a pin 103, in accordance with the prior art. The core is capable of communicating data to a tri-state output buffer 105 and receiving data via an input buffer 107.
FIG. 2 is an illustration showing a partial circuit design 100B after BS cells have been inserted to incorporate JTAG logic into the circuit design, in accordance with the prior art. In this example, three types of BS cells 201, 203, and 205 are used to perform control, output, and input functions, respectively. While the BS cells 201, 203, and 205 provide benefit with respect to enhancing testability, insertion of the BS cells 201, 203, and 205 into the circuit design can introduce adverse timing and skew issues. More particularly, FIGS. 3 and 4 highlight some adverse timing and skew issues associated with insertion of prior art output BS cells.
FIG. 3 is an illustration showing an output BS cell 300, in accordance with the prior art. The output BS cell 300 includes a synchronous flip-flop 301 in communication with a multiplexer (MUX) 303. The synchronous flip-flop 301 includes a data input port D for receiving a data input signal DI and a data output port Q for transmitting an output signal. Also, the synchronous flip-flop 301 includes a clock input port 305 for receiving a system clock signal clk. The output signal is transmitted from the data output port Q of the synchronous flip-flop 301 to a first input of the MUX 303. An output from the MUX 303 is connected to the tri-state output buffer 105, which is in turn connected to the I/O pin 103. Additionally, a test data input TDI is connected from an output of a test access port (TAP) controller to a second input of the MUX 303. The TAP controller receives a test mode select TMS signal and a test clock signal TCK as inputs. The TAP controller logic complies with the IEEE Standard 1149.1.
During normal mode operation, the output BS cell 300 will transmit the data input signal DI maintained in the synchronous flip-flop 301 through the MUX 303 to the tri-state output buffer 105 in accordance with the system clock signal clk. During test mode operation, the output BS cell 300 will transmit the test data input signal TDI through the MUX 303 to the tri-state output buffer 105 in accordance with the test clock signal TCK. The MUX 303 serves to ensure that the proper signal DI or TDI is transmitted to the tri-state output buffer 105 depending on whether the output BS cell 300 is operating in normal mode or test mode, respectively.
While the output BS cell 300 enables boundary scan testing, the output BS cell 300 also adversely affects delay and skew associated with a functional path of data input signal DI to the tri-state output buffer 105 and ultimately the I/O pin 103. The adverse delay and skew effects are caused by insertion of the MUX 303 between the synchronous flip-flop 301 and the tri-state output buffer 105.
Functional path delay is increased by the MUX 303 itself along with additional wire length required to insert the MUX 303. In many cases, a specific amount of time is allowed for getting data out of the I/O pin 103 from when the system clock signal clk is received at the clock input port 305. The additional delay introduced by the MUX 303 can be detrimental in these cases.
Furthermore, skew can be introduced by differences in wire lengths associated with connection of the MUX 303 in various output BS cells 300 around the chip. In other words, differences in wire lengths both before and after the MUX 303, respectively, between the various output BS cells 300 can introduce skew. Some prior art methods for minimizing the skew associated with placement of the MUX 303 have included hand-placing each MUX 303 and developing a macro to place each MUX 303. Though somewhat effective for minimizing skew, these prior art methods do require time, effort, and expense. Also, once the skew issue is minimized, the delay issue remains in full effect.
FIG. 4 is an illustration showing an output BS cell 400, in accordance with the prior art. The output BS cell 400 includes the synchronous flip-flop 301 in communication with a data MUX 401. The data MUX 401 is placed before the synchronous flip-flop 301. As previously mentioned, the synchronous flip-flop 301 includes a data input port D for receiving an input signal and a data output port Q for transmitting an output signal. In the output BS cell 400, the input signal received at the data input port D can be one of the data input signal DI or the test data input signal TDI, depending on the data MUX 401. Also, the synchronous flip-flop 301 includes the clock input port 305 for receiving a clock signal. In the output BS cell 400, the clock signal received at the clock input port 305 can be one of the system clock signal clk or the test clock signal TCK, depending on a clock MUX 403. The output signal is transmitted from the data output port Q of the synchronous flip-flop 301 to the tri-state output buffer 105, which is in turn connected to the I/O pin 103. Additionally, the test data input signal TDI is provided from the TAP controller to a first input of the data MUX 401. Also, a data input signal DI is provided to a second input of the data MUX 401. As previously mentioned, the IEEE Standard 1149.1 TAP controller receives the test mode select TMS signal and the test clock signal TCK as inputs.
During normal mode operation, the data MUX 401 is set to transmit the data input signal DI, and the clock MUX 403 is set to transmit the system clock signal clk. In following, the output BS cell 400 transmits the data input signal DI maintained in the synchronous flip-flop 301 to the tri-state output buffer 105 in accordance with the system clock signal clk. During test mode operation, the data MUX 401 is set to transmit the test data input signal TDI, and the clock MUX 403 is set to transmit the test clock signal TCK. In following, the output BS cell 400 transmits the test data input signal TDI maintained in the synchronous flip-flop 301 to the tri-state output buffer 105 in accordance with the test clock signal TCK.
As with the output BS cell 300 discussed with respect to FIG. 3, the output BS cell 400 also adversely affects delay and skew associated with the functional path of the data input signal DI to the tri-state output buffer 105 and ultimately the I/O pin 103. However, in the case of the output BS cell 400, the adverse delay and skew effects are caused by insertion of both the data MUX 401 and the clock MUX 403, for reasons similar to those described with respect to the output BS cell 300 of FIG. 3.
In view of the foregoing, there is a need for boundary scan apparatus that can be easily incorporated into integrated circuit designs without introducing adverse delay and skew characteristics which could negatively affect either a functional data path or a timing path.